Lumped element digital phase shifter bit

ABSTRACT

Digital phase shifter bits of predetermined phase shift capability and lumped element network component fabrication arrangement are described. A variety of phase shifter bits including the capability of eleven and one-quarter, twenty-two and one-half, forty-five, ninety, and one hundred eighty degrees of phase shift are included. Also included are a number of high-pass/low-pass and switching transistor inclusive phase shifter bit arrangements. Both electrical schematic diagram and integrated circuit embodiments of the phase shifting networks are also disclosed.

RIGHTS OF THE GOVERNMENT

The invention described herein may be manufactured and used by or forthe government of the United States for all governmental purposeswithout the payment of any royalty.

BACKGROUND OF THE INVENTION

This invention relates to the field of integrated circuit electronicnetworks providing selectable degrees of signal phase shift at microwaveoperating frequencies.

Phased array radar antennas and other microwave apparatus have need ofdigitally selectable phase delaying networks which are both low infabrication cost and of the smallest possible physical size. Foroperating frequencies above ten gigahertz the use of distributedcomponents in these phase shifting networks has become an accepteddesign practice in the microwave art. For frequencies below tengigahertz, however, distributed component phase shifting components suchas quarter wavelength microstrip delay lines become prohibitively longin physical size for implementation on an integrated circuit chip. Inaddition to the difficulty of containing these large phase shiftingnetwork components in an electronic apparatus--an apparatus which isalmost always limited in physical size--the cost of fabricating theseunduly large sized networks is found to be directly related to thephysical size of the integrated circuit chip used to contain the networkso that the large size in itself promotes undesirable apparatus cost.

The prior patent art includes several examples of previous phaseshifting network practices. Included in these prior patents is the U.S.Pat. No. 4,471,329 of E. C. d'Oro which concerns a microstrip waveguidestructure; the U.S. Pat. No. 4,471,330 of Naster et al which shows aconventional digital phase shifting bit that incorporates high frequencytransmission lines; the U.S. Pat. No. 4,556,808 of Coats in whichintegrated lumped element pi-networks replace quarter wavelengthtransmission lines in a switching circuit arrangement; the U.S. Pat. No.4,612,520 of Borie et al which describes a wideband 180 degree phaseshifter bit that includes both transmission line segments and api-network; the U.S. Pat. No. 4,630,010 of Yarman which shows a low passdigital phase shifter for use at extra high frequencies; and the U.S.Pat. No. 4,652,883 of Andricos which concerns a signal phase shifter foruse in a phased array radar system. None of these prior patents,however, achieves the advantages of the lumped element digital phaseshifter bit of the present invention.

SUMMARY OF THE INVENTION

The present invention achieves both a physical size reduction and afabrication cost reduction in the realization of certain microwave phaseshifting elements through the use of lumped electrical elements as areplacement for the distributed elements normally used in such networks.The invention is also related to phase shifting networks in which adigital control signal can be used to alter the achieved degree of phaseshift between discrete predetermined values.

It is an object of the invention therefore to provide a phase shiftingnetwork arrangement which is of desirable low cost and small physicalsize.

It is another object of the invention to provide a phase shiftingnetwork realization arrangement which is especially advantageous for usein the lower frequency portion of the microwave spectrum.

It is another object of the invention to provide a plurality ofalternate phase shifting network circuit configurations which may beembodied in discrete or lumped element integrated circuit form.

It is another object of the invention to provide discrete component orlumped element integrated circuit phase shifting networks in which abinary control signal and switching transistor elements are selective ofdifferent network frequency response characteristics.

It is another object of the invention to provide lumped element phaseshifting networks which may be readily configured to a plurality ofdifferent phase shift values.

Additional objects and features of the invention will be understood fromthe following description and the accompanying drawings.

These and other objects of the invention are achieved by integratedcircuit digital phase shifter apparatus for use at microwave signalfrequencies below ten gigahertz which includes the combination of; anintegrated circuit die member having a semiconductor body portion and anupward facing planar surface; a plurality of discrete electricalinductance elements disposed in predetermined physical location arrayacross said die member upward facing planar surface; a plurality ofdiscrete electrical capacitance elements disposed in predeterminedphysical location array across said upward facing planar surface of saiddie member in predetermined phase shifting electrical networkinterconnection with said electrical inductance elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a plurality of electrical networks which may be used in thepresent lumped element phase shift invention.

FIG. 2 shows an integrated circuit realization of one FIG. 1 networkconfiguration 108 herein, as arranged for one specific degree of phaseshift (11.25°).

FIG. 3 shows an integrated circuit realization of one FIG. 1 network asarranged for a second degree of phase shift (22.5°).

FIG. 4 shows an integrated circuit realization of one FIG. 1 network asarranged for a third degree of phase shift (45°).

FIG. 5 shows a two path pi-configured phase shifting network including apair of path selecting transistor switching arrays.

FIG. 6 shows a lumped element integrated circuit embodiment of the FIG.5 network as arranged for 90 degrees of phase shift.

FIG. 7 shows a lumped element integrated circuit embodiment of the FIG.5 network arranged for 180 degrees of phase shift.

FIG. 8 shows a simplified phase shift bit circuit which is useful at lowvalues of phase shift.

FIG. 9 shows an alternate phase shift network arrangement which may berealized according to the present invention.

FIG. 10 shows a table of values for embodying one arrangement of theFIG. 1 network circuits as integrated circuit devices.

FIG. 11 shows a table of values for embodying the network of FIG. 5 asan integrated circuit.

DETAILED DESCRIPTION

FIG. 1 in the drawings shows a collection of seven tee and pi configuredelectrical networks which may be embodied as microwave phase shiftingdevices using the lumped element concept of the present invention. Eachof the different network configurations 100, 102, 104, 106, 108, 110,and 112 in FIG. 1 employs a plurality of inductive, capacitance, andtransistor elements which are provided with selected electrical valuesin order to achieve a predetermined degree of microwave signal phaseshift between the input and output terminals of the network.

In the FIG. 1 drawing the transistor element in each of the differentnetworks are indicated by the circle having an inscribed x as isindicated at 120 and 122 in the network configuration 108, for example.Preferably these transistor are of the field effect type and arefabricated directly onto the surface of the host integrated circuitdevice using one of the known transistor fabrication technologies.Typically, transistors of this type may have a turned on resistancewhich is in the range of 0.54 ohm-centimeters, a turned off resistanceand capacitance combination of 0.36 ohm-centimeter and 1.72 picofaradper centimeter.

In view of the differing number of s-plane analysis poles and zeros andthe otherwise differing electrical configurations of the networks shownin FIG. 1, variations in the change of signal phase delay with frequencycan be expected with differing ones of the FIG. 1 configurations. One ofthe FIG. 1 configurations, the configuration 108, is believed typicaland is selected for embodiment in the FIGS. 2-4 illustrated phase shiftcircuits.

The configuration 108 includes the two transistors 120 and 122 which areconnected in shunt with the inductive elements 114 and 116 and thisshunt combination as is connected in series with the capacitanceelements 124 and 126; the junction between the capacitance elements isconnected to the network common terminal by the shunt combination of theinductance 118 and the capacitance 128. A table of values for these andother FIG. 1 inductive and capacitance elements, using the C and Lsubscripted numeral identifications and the circuit identificationsshown in FIG. 1, appears in the Table 1 of FIG. 10 in the drawings.Although the network configuration 108 and indeed all of the networkconfigurations shown in FIG. 1 may be tailored for use at any number ofdifferent frequencies, the table of values shown in FIG. 10 presumes usein the "L" band or 1.3 gigahertz frequency range.

As is indicated by the numerical values in the left most column of thetable 1 in FIG. 10, varying predetermined amounts of phase shift are tobe realized from the use of different values in the networkconfiguration 108. The numbers between 100 and 112 along the top mostportion of FIG. 10, of course, identifies the differing networkconfigurations shown in FIG. 1. The column of numbers in the seventhcolumn from the left hand edge in FIG. 10 is particularly applicable tothe network configuration 108 in FIG. 1. The shunt capacitor 128 in thenetwork configuration 108 is shown in Table 1 to have a electrical valuebetween 1.0 and 2.2 picofarads according to the desired value of phaseshift being ninety or eleven and one quarter or some intermediate numberof electrical degrees.

The size or magnitude of the component values recited in Table 1 suggestthat the network configuration 108 is one of the more desirable of theconfigurations shown in FIG. 1 for realization in the form of anintegrated circuit network. A comparison of the component values shownin Table 1, for example, shows that indicators in the range of 1.1 to9.9 nanohenrys are required for phase shifts between 11.25 and 90degrees and capacitances of 1.6 to 20.5 picofarads are required. Forother of the FIG. 1 networks, however, the required inductor sizes maybe as large as 33, 43 or even 61 nanohenrys. In a practicalenvironmental it is found that inductances above 20 nanohenrys andcapacitances less than 0.1 picofarad are difficult to fabricate asintegrated circuit elements. The moderate range of the configuration 108values recited in Table 1 therefore make this network a desirable choicefor the present usage.

By way of including the switching transistor devices 120 and 122 in thenetwork configuration 108 of FIG. 1 this network is provided with thecapability of operating as either a series loaded line phase shifter. Aloaded line phase shifter serves to periodically load a transmissionline with alterable reactances to achieve phase shift. The periodicityof the reactance is nominally a quarter wavelength to properly cancelmismatches introduced by the reactive loads.

In the various configurations in FIG. 1, a single quarter wavelengthsection is used with reactive loading being located at each end. Forthis invention, the distributed quarter wavelength transmission line isin fact replaced by a lumped element equivalent circuit which consistsof capacitors and inductors (in FIG. 1 these are represented by L₁, L₂,C₁, and C₂). The loading reactance is achieved by the parallelcombination of the switching device or switching transistor and aparallel inductor and/or capacitor (in the configurations of FIG. 1these are represented by L₃ and C₃). The switching device is used toalter the loading reactance and therefore alter the phase through thecircuit. The amount of phase shift is proportional to the amount ofreactance change.

The switching devices shown in FIG. 1 are preferably embodied as fieldeffect transistors (FETs)--a three terminal device with terminalsdesignated as gate, drain, and source. The FET when operated as a switchuses the gate to modulate the conductance between the source and drain.The conditions for operating the FET as a microwave switch require thesource and drain to each have an applied DC potential of zero volts andthe gate have an applied DC potential of either zero volts or a negativeDC potential. The FET as a switch is considered "on" when the gatepotential is zero whereby the microwave signal applied to the drain ispassed to the source with minimal alteration. The FET as a switch isconsidered "off" when the applied gate potential is beyond the devicepinchoff voltage (usually -5V) which causes significant microwave signalattenuation when passing from the drain to the source. Since the FETwhen operated as a switch is bilateral in nature, the microwave signalcan be applied to either the drain or the source terminals.

FIGS. 2, 3, and 4 in the drawings show integrated circuit chipembodiments of the network configuration 108 in FIG. 1 with each ofthese embodiments resulting in a different amount of phase shift to anapplied L band microwave signal. The FIG. 4 forty-five degree phaseshift embodiment of the network 108 is typical of the FIGS. 2-4 circuitdevices and is described in some detail herein along with appropriatereferences to the other two figures.

In view of the glossy photographic print nature of the FIG. 4 drawing inthe present application, document references to individual portions ofthe FIG. 4 network are accomplished with an array of coordinatedreference numbers, the numbers between 402 and 430 in FIG. 4, ratherthan with the usual number attached to a lead line arrangement. In theFIG. 4 integrated structure, for example, the spiral configuredconductors centered at the intersection of the coordinates 402 and 404represents the inductance L1, 118 in the FIG. 1 drawing. In a similarmanner the node at the intersection of the coordinates 402 and 406 inFIG. 4 represents the lower or common conductor 130 in FIG. 1. Thecapacitor C1 at 128 in FIG. 1 is shown at the intersection of thecoordinates 406 and 432 in FIG. 4 while the transistor 120 in FIG. 1 isshown at the intersection of coordinates 416 and 420 and the transistor122 at the intersection of coordinates 416 and 418 in FIG. 4.

It should be noted that the position of the capacitor C2 at 126 in FIG.1 and the shunt combination of the inductance 116 and transistor 122 areinterchanged in the network embodiment of FIG. 4. As is known in theelectrical network art, the interchanging or interposition of seriesconnected electrical components has no effect on the electricalproperties of the network. In a similar manner the position of thecapacitor C2 at 124 and the inductor 114 and transistor 120 areinterchanged in the FIG. 4 circuit arrangement.

Continuing then with the correlation of components in FIGS. 1 and 4, theinductor L3 at 114 in FIG. 1 is shown at the intersection of thecoordinates 420 and 422 in FIG. 4 while the inductor L3 at 116 in FIG. 1resides at the intersection of the coordinates 418 and 422 in FIG. 4.The capacitor C2 at 124 appears at the 404-416 coordinate intersectionin FIG. 4 while the capacitor C2 at 126 appears at the coordinateintersection 408-416.

The portions of the FIG. 4 embodiment lying at the coordinateintersections 414-412 and 434-412 comprise electrical resistances whichare not shown in the FIG. 1 schematic diagram but which are connected inelectrical series with the transistor gate terminals in order to isolatethe radio frequency and DC level control signals which exist in thetransistors 120 and 122. DC resistance values in the range of 2000 ohmsare found appropriate for this isolation. As is indicated in the upperleft hand corner of the FIG. 4 embodiment, at the intersection of thecoordinates 428 and 430, the phase shifting circuitry of FIG. 4 isintended to provide a phase shift of 45 degrees at L-band operatingfrequency.

The integrated circuit substrate which is indicated at 400 in FIG. 4 maybe fabricated from one of the known semiconductor material, however,gallium arsenide is the preferred material. At 408-410 in FIG. 4 islocated a gate control connection by which the digital signalscontrolling transistor operation is received onto the integrated circuitchip. The output terminals of FIG. 4 network are shown at the extremeleft and right edges of the circuit chip in line with the coordinate416.

Except for electrical values and resulting changes in discrete componentphysical sizes, the eleven and one quarter degree and twenty two and onehalf degree phase shifting networks embodied in FIG. 2 and FIG. 3 aresimilar to the above described FIG. 4 embodiment.

FIG. 5 in the drawings shows a high-pass/low-pass phase shifting networkthat is combined with a pair of transistorized single pole double throwswitches. The transistorized switches are located at the input andoutput terminals of the FIG. 5 network. In the FIG. 5 circuit thehigh-pass network is located at 516 in the top arm of the circuit whilethe low-pass network is at 518 in the lower arm of the network and theinput transistor switches is located at 504 and the output switch at506. The network input terminals 500 is shown coupled to a pair ofseries pass field effect transistors 508 and 510 and the signal emergingfrom these series pass transistors is shunted by the two crowbartransistors 512 and 514. A similar transistor switching arrangement isshown at 506 adjacent the output terminal 502.

During operation of the FIG. 5 circuit it is contemplated that two ofthe series pass transistors such as the transistors 508 and 520 and twoof the crowbar transistors such as the transistors 514 and 524 will bemaintained in the conducting conditions by application of a suitablevoltage at the node 526--in order to make use of the high-pass phaseshifting network 516. Alternately, for use of the low-pass network 518the transistors 510, 522, 512, and 528 will be placed in the conductingcondition by a suitable voltage to the node 530.

Underlying the FIG. 5 circuit is the concept that a low-pass filtercomprised of series inductors and shunt capacitors provide phase delayto signals passing through it. A high-pass filter comprised of seriescapacitors and shunt inductors similarly provides phase advance. Byarranging switches to permit switching between the low-pass andhigh-pass configurations, a phase shifter can be made which is smallerthan the other types while also achieving good bandwidthcharacteristics. A table of values for the FIG. 5 circuit operating atL-band frequencies is shown in FIG. 11, Table 2 of the drawings.

By way of acknowledgement, in addition to the lumped element concept ofthe present invention, certain aspects of FIG. 5 as well as FIGS. 6 and7 also relate to an invention described in application Ser. No.07/110,015 by Anthony Jacomb-Hood. Additional aspects of the FIGS. 5, 6,and 7 network are also described in the technical article "AffordableMMIC Designs for Phased Arrays" authored by Ronald J. Naster, AnthonyJacomb-Hood, and Mark R. Lang and published in the March 1977 issue of"Microwave Journal", a publication of Horizon House-Microwave, Inc.

FIG. 7 in the drawings shows a microphotograph of an integrated circuitembodiment of the FIG. 5 phase shifting network--an embodiment using thelumped element components of the present invention. With exception ofthe transposed locations for the inductor at 711, 712 and the groundingpad at 710, 711 in FIG. 7, the presence of the crowbar transistors at716, 717 and 717, 718 and presence of the uppermost or low-pass portionof the circuit at 714, the components in the FIG. 7 integrated circuitchip are similarly disposed and identified as was discussed inconnection with the FIG. 4 chip above.

The FIG. 7 circuit die represents a 180 degree phase shift embodiment ofthe high-pass/low-pass network arrangement indicated at 720, 721 in FIG.7. A ninety degree phase shift arrangement of this high-pass/low-passphase shift bit is also shown in FIG. 6 of the drawings. The FIG. 6circuit chip is very similar to the FIG. 7 circuit and differs therefromprincipally in size and physical arrangement of the inductance at 602,603 and the capacitors at 604, 605 and 605, 606.

The high-pass/low-pass circuit arrangement of FIG. 7 (i.e., the 180° bitcircuit) is found to have significantly lower process sensitivity thenis a high-pass/low-pass circuit arrangement in which switch capacitanceis integrated into the filter network. These conventional circuits alsorequire less chip area and have slightly higher insertion losses.

For low values of phase shift, that is, for phase shifts in the order ofeleven degrees or less, the single resonated FET bit design shown inFIG. 8 of the drawings may be used. In the FIG. 8 phase shifter, theinherent capacitances of the FET transistor 802 are resonated with theshunting inductance 804 to provide a small value of phase shift. Theresonated FET phase shifter of FIG. 8 is found to provide a phasedifference that is proportional to frequency, a condition that isacceptable for lower values of phase shift.

FIG. 9 in the drawings shows an other phase shifter bit circuitarrangements which may be used with the present discrete element circuitembodiments and which relate in a plurality of ways to the herebeforedescribed circuit arrangement. In the FIG. 9 drawing is shown anarrangement of the FIG. 5 circuit wherein transistor switches areincluded in the switched filter sections and in which the off statecapacitance of the FET switches is less limiting then in the FIG. 5circuit 15.

For the ninety degree, forty-five degree, and twenty- two and one-halfdegree phase shifter bits, the simplified high-pass/low-pass design ofFIG. 9 with integrated switches is a desirable circuit approach. Thiscircuit is the least sensitive to process variations and requires theleast chip area (except for the twenty-two and one-half degree bit). Thetwenty-two and one-half degree bit is significantly larger than theseries loaded-line design, but its achievable higher processing yieldmore than outweighs the decrease in unit area yield caused by the largerchip size. The variations in phase angle across the band is alsoextremely small for these arrangements, as is the difference ininsertion loss between states. Furthermore, all the element valuesrequired by these circuits are easily realized in monolithic MicrowaveIntegrated Circuit (MMIC) form. For the ninety degree and forty-fivedegree bits, the conventional high-pass/low-pass approach is slightlymore lossy, slightly larger and slightly more process sensitive. Theprimary eleven and one-quarter degree bit is a simple resonated FETsince this circuit has good process variation tolerance and lowinsertion loss and is small in size. A simplified low-pass/high-passdesign is not possible for these bits because of the large inductancevalues associated with this type of design.

With the lumped element arrangement described herein for the phaseshifter bit, significant decreases in physical size, decreases in therange of six to one, can be achieved. In addition to this reduced sizeand its benefits from the equipment packaging view point the reducedarea in such circuits amounts to a significant cost decrease. Thereduced area also increases the integrated circuit fabrication yield.These circuits also achieve greater tolerance to process variations andare associated with greater testability and ease of assembly.

While the apparatus and method herein described constitute a preferredembodiment of the invention, it is to be understood that the inventionis not limited to this precise form of apparatus or method and thatchanges may be made therein without departing from the scope of theinvention which is defined in the attended claims.

We claim:
 1. Integrated circuit digital phase shifter apparatus for useat microwave signal frequencies below ten gigahertz comprising thecombination of:an integrated circuit die member having a semiconductorbody portion and an upward facing planar surface; a plurality ofdiscrete electrical inductance elements disposed in predeterminedphysical location array across said die member upward facing planarsurface; and a plurality of discrete electrical capacitance elementsdisposed in predetermined physical location array across said upwardfacing planar surface of said die member in predetermined phase shiftingelectrical network interconnection with said electrical inductanceelements.
 2. The phase shifter apparatus of claim 1 wherein said phaseshifting electrical network generates one of the phase shift values ofeleven and one quarter degrees, twenty-two and one-half degrees,forty-five degrees, ninety degrees, and one hundred eighty degrees at apredetermined frequency below said ten gigahertz frequency.
 3. The phaseshifter apparatus of claim 1 further including a plurality of phaseshifter selecting transistor switch members connected in predeterminedelectrical circuit with said electrical inductance and electricalcapacitance elements.
 4. The phase shifter apparatus of claim 3 whereinsaid transistor switch members comprise field effect transistors.
 5. Thephase shifter apparatus of claim 3 wherein said transistor switchmembers comprise electrical shunting means connected across pluralelements of said network for altering the network frequency response. 6.The phase shifter apparatus of claim 3 wherein said transistor switchmembers are connected into a single pole double throw switchconfiguration.
 7. The phase shifter apparatus of claim 1 wherein saidelectrical inductance elements and electrical capacitance elementscomprise one of a tee configured and a pi-configured network.
 8. Thephase shifter apparatus of claim 1 wherein said electrical inductanceelements include concentric circle spiral disposed conductors receivedon said die surface.
 9. The phase shifter apparatus of claim 1 whereinsaid electrical network comprises both a low-pass and a high-passfrequency selective network.
 10. The phase shifter apparatus of claim 1wherein said phase shifting electrical network comprises a threeterminal electrical network.
 11. The phase shifter apparatus of claim 1further including a pi configured electrical network wherein the stemportion of the pi network includes shunt connected inductance andcapacitance elements, and the input and output arms of the pi networkinclude series connected inductance and capacitance elements.
 12. Thephase shifter apparatus of claim 11 wherein said input and output arminductive elements are shunted by field effect transistors.
 13. Thephase shifter apparatus of claim 1 further including an input circuitnode and an output circuit node and first and second circuit pathsconnecting said nodes with each of said circuit paths including acombination of electrical reactance elements and field effect transistorelements.